Excellent real world experience with FPGA logic design using Verilog and
VHDL. Proven ability to solve difficult problems while implementing novel approaches and reducing
cost. Expert in high speed data transfer and Digital Signal Processing. High speed
asynchronous data recovery, Software Defined Radios(SDR), all-digital phase locked loops, signal
integrity (SI), power integrity (PI), PCI and PCIexpress host bus adapters. High level languages
include Matlab, Simulink, Octave and Python, for system behavioral modeling and problem solving.
We know: Xilinx and Altera FPGAs and design environments, Verilog, Mentor Graphics (ModelSim) mixed
mode HDL simulator, Matlab, Octave, Python, Hyperlynx SI/PI simulator, Ansoft / Ansys SiWave FEA
Field Solvers, HFSS, SPICE, Orcad, Mathcad, Matlab, Simulink, Octave.